`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:35:49 11/29/2011 
// Design Name: 
// Module Name:    PongGame 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module PongGame(clk, reset_MSTR, invert, vga_h_sync, vga_v_sync, R, G, B, SW0, SW1, SW2, h_1bit, v_1bit, R_1bit, G_1bit, B_1bit, latch, latch2, pulse, pulse2, data, data2, SF_D, LCD_E, LCD_RS, LCD_RW, plyr2_input, songNote);
 
input reset_MSTR;
input SW0, SW1, SW2;
input invert;
input clk;
output vga_h_sync, vga_v_sync;
output [2:0] R, G;
output [1:0] B;
output [11:0] plyr2_input;
//CPU, the cpu is initialized with the assembly code inside the IM - RAM module that controls the pon game movements
wire [11:0] plyr_input;
wire [11:0] plyr2_input;
wire [9:0] objX; 
wire [8:0] objY;
wire [3:0] tile;
wire [9:0] pixelX;
wire [8:0] pixelY;
wire [9:0] ballx;
wire [8:0] bally;
wire [8:0] p1;
wire [8:0] p2;
wire pauseclk;
reg pause;

output R_1bit, G_1bit, B_1bit, h_1bit, v_1bit;
assign v_1bit = vga_v_sync;
assign h_1bit = vga_h_sync;
assign R_1bit = R[2];
assign G_1bit = G[2];
assign B_1bit = B[1];

reg reset;
CPU_Pipelined CPU(clk, reset_MSTR, ballx_pause, bally_garbage, p1, p2, plyr_input, plyr2_input, garbage, garbage2);

//Refresh rate?
wire refreshRate;
clkDivider refreshRateScreenObjects(clk, refreshRate, reset_MSTR); //reset always == 0
defparam  refreshRateScreenObjects.BITS = 32;
defparam  refreshRateScreenObjects.maxcount = 12500000;//answers rounded up/down
//defparam   oneFourthSecond.maxcount = 1; // for simulation testing

wire puaseButtonRate;
clkDivider ButtonRate(clk, puaseButtonRate, reset_MSTR); //reset always == 0
defparam  ButtonRate.maxcount = 5000000;//answers rounded up/down
//defparam   oneFourthSecond.maxcount = 1; // for simulation testing

//LCD Writer
output [11:8] SF_D;
output LCD_E;
output LCD_RS;
output LCD_RW;
lcd_ctrl LCD(clk, reset, {p1_score, 8'hFF, p2_score}, SF_D, LCD_E, LCD_RS, LCD_RW);

//VGA Controller

VGAController VGA(clk, invert, reset_MSTR, plyr_input, plyr2_input, vga_h_sync, vga_v_sync, R, G, B, pixelX, pixelY, tile, draw_enable, objX, objY, refreshRate);
//Collision VGA
collisionDetection gameObjectsDrawer(clk, pixelX, pixelY, objX, objY, ballx, bally, p1, p2, tile, draw_enable);

reg pauseEnabled = 0, resetEnabled = 0;
BallMovement ballMove(clk, resetEnabled, pauseEnabled, ballx, bally, p1, p2, plyr_input, plyr2_input, p1_score, p2_score, enableSound);//ballx_pause
//SNES controllers
output latch,pulse, latch2,pulse2;
input data, data2;
SNESController SNES_P1(clk, 1'b0, latch, pulse, data, plyr_input);
SNESController SNES_P2(clk, 1'b0, latch2, pulse2, data2, plyr2_input);

//Sound
playNote Note(clk, enableSound, reset, note);
reg [31:0] countTotal = 12500001;
reg [31:0] curCount = 0;

output songNote; //sound frequency clock
always@(posedge clk) begin
if(enableSound)
	curCount <= 1;
if(curCount != 0) begin
	if(countTotal == curCount) begin
		songNote <= 0;
		end
	else  begin
		songNote <= note; end
end
end

always @(posedge puaseButtonRate) begin
//clk speed for switching tiles.... ~1/4 a second == Every 12.5MHz completed increase if needed.

	 
	 
	 if(plyr_input[8] | plyr2_input[8]) begin //select button -> restart
		 if(pauseEnabled)
								pauseEnabled <= 0;
		  else begin
								pauseEnabled <= 1;
		  end
	 end
	 else if(plyr_input[9] | plyr2_input[9]) begin //select button -> restart
		  
								resetEnabled <= 1;
	 end
	 else begin 
		resetEnabled <=0;
	end
	 
end


endmodule
